`include "defines.v"

module Hazard_Detection (
    input wire [ 4: 0] rs1_addr,
    input wire [ 4: 0] rs2_addr,
    input wire [ 4: 0] rd_addr_ex,
    input wire [ 4: 0] rd_addr_mem,
    input wire MemToReg_ex,
    input wire MemToReg_mem,
    output wire load_use_stall,

    input wire pc_sel,
    output wire flush
);
wire load_use_stall_ex;
wire load_use_stall_mem;
//load-use hazard   ->  2 cycles delay
assign load_use_stall_ex = (rs1_addr == rd_addr_ex || rs2_addr == rd_addr_ex) && (|rd_addr_ex) && MemToReg_ex;
assign load_use_stall_mem = (rs1_addr == rd_addr_mem || rs2_addr == rd_addr_mem) && (|rd_addr_mem) && MemToReg_mem;
assign load_use_stall = load_use_stall_ex | load_use_stall_mem;

//B/J type inst flush
assign flush = pc_sel;

endmodule